Electrical characteristics
Table 15. Output pin transition times (continued)
Symbol
C
Parameter
Conditions1
Value2
Unit
Min
Typ
Max
Ttr
CC
D
Output
CL =
VDD =
—
—
4
ns
transition 25 pF 5.0 V ±
time output
pin3
CL =
10%,
PAD3V5V
—
—
6
FAST
50 pF
=0
configurati CL =
on
100 pF
—
—
12
CL =
VDD =
—
—
4
25 pF 3.3 V ±
10%,
CL =
PAD3V5V
—
—
7
50 pF
=1
CL =
100 pF
—
—
12
1 VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified
2 All values need to be confirmed during device validation.
3 CL includes device and package capacitances (CPKG < 5 pF).
3.6.5 I/O pad current specification
The I/O pads are distributed across the I/O supply segment. Each I/O supply segment is associated to a VDD/VSS supply pair as
described in Table 16.
Table 17 provides I/O consumption figures.
In order to ensure device reliability, the average current of the I/O on a single segment should remain below the IAVGSEG
maximum value.
In order to ensure device functionality, the sum of the dynamic and static current of the I/O on a single segment should remain
below the IDYNSEG maximum value.
Table 16. I/O supply segments
Supply segment
Package
1
2
3
4
5
6
208
MAPBGA1
Equivalent to 176 LQFP segment pad distribution
176 LQFP pin7– pin27 pin28 –
pin57
pin59 –
pin85
pin86 –
pin123
144 LQFP pin20 – pin51 – pin100 – pin 123 –
—
—
pin49
pin99
pin122
pin19
100 LQFP pin16 – pin37 – pin70 – pin84 –
—
—
pin35
pin69
pin83
pin15
1 208 MAPBGA available only as development package for Nexus2+
7
MCKO
pin124 –
pin150
—
8
MDOn
/MSEO
pin151 –
pin6
—
—
—
MPC5607B Microcontroller Data Sheet, Rev. 3
24
Freescale Semiconductor
Preliminary—Subject to Change Without Notice