SPT5420 View Datasheet(PDF) - Cadeka Microcircuits LLC.
Part Name
Description
MFG CO.
'SPT5420' PDF : 8 Pages View PDF
TIMING CHARACTERISTICS
Figure 1a – Timing Diagram: Latched Mode
(LDAC Strobed)
t1
t2
Figure 1b – Timing Diagram: Transparent Mode
(LDAC Held Low)
t1
t2
A0A2
CS
WR
D0D12
t3
t5
t6
t4
t7
t8
t9
VOUT
A0A2
CS
WR
D0D12
VOUT
t3
t5
t6
t4
t7
t8
t9
LDAC
t10
t11
CLR
t9
VOUT
PARAMETER
SYMBOL MIN TYP MAX UNIT
Address Valid to WR Setup t1
20
ns
Address Valid to WR Hold
t2
0
ns
CS Pulse Width Low
t3
50
ns
WR Pulse Width Low
t4
50
ns
CS to WR Setup
t5
0
ns
WR to CS Hold
t6
0
ns
Data Setup
t7
25
ns
Data Hold
Settling Time1
t8
0
t9
ns
15 us
LDAC Pulse Width Low
t10
50
ns
CLR Pulse Activation
t11
NOTES:
300 ns
All digital input rise and fall times are measured from 10% to 90% of +5 V.
tr = tf = 5 ns.
1. RL = 10 kΩ
CL ≤ 220 pF
SPT5420
4
6/26/01
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