SPT5420 View Datasheet(PDF) - Cadeka Microcircuits LLC.
Part Name
Description
MFG CO.
'SPT5420' PDF : 8 Pages View PDF
PIN ASSIGNMENTS
RGND01
VOUT0
VREFB01
VREFT01
VDD
VSS
LDAC
A2
A1
A0
CS
44
1
Top View
RGND67
VOUT7
VREFB67
VREFT67
VSS
CLR
D12 (MSB)
D11
D10
D9
D8
PIN FUNCTIONS
Name
Function
DIGITAL CONTROL PINS
CS
Chip Select (Active Low)
WR
Level Triggered Write Input (Active Low). Used in
conjunction with CS to write data to the SPT5420
input data latches. Data is latched into selected
input data latch on the rising edge of WR.
CLR
(Active Low) Analog Clear. Sets the output
voltages to RGND. (Each RGND is common to a
DAC pair.) CLR does not reset the digital latches.
When CLR is brought back high, the DAC outputs
revert back to their original outputs as determined
by the data in their DAC latches.
LDAC
When this logic input is taken low, the contents of
the input latches are transferred to their respective
DAC latches. (Active Low) Data is latched on
rising edge.
A0 – A2 Addresses DAC0 to DAC7 for loading the eight
input latches.
D0 – D12 Digital Inputs (D0 = LSB)
ANALOG PINS
VREFT01 Top Reference Voltage for DACs 0 and 1
VREFT2345 Top Reference Voltage for DACs 2, 3, 4 and 5
VREFT67 Top Reference Voltage for DACs 6 and 7
VREFB01 Bottom Reference Voltage for DACs 0 and 1
VREFB2345 Bottom Reference Voltage for DACs 2, 3, 4 and 5
VREFB67 Bottom Reference Voltage for DACs 6 and 7
RGND01 Reference Ground for Output Amplifiers 0 and 1
RGND23 Reference Ground for Output Amplifiers 2 and 3
RGND45 Reference Ground for Output Amplifiers 4 and 5
RGND67 Reference Ground for Output Amplifiers 6 and 7
VOUT0–7 Output Voltage Pins for DAC0 – DAC7
POWER SUPPLY PINS
VCC
Digital +5 V Supply
VDD
Analog +11.5 V Supply (Nominal)
VSS
Analog –8 V Supply (Nominal)
GND
Ground
ORDERING INFORMATION
PART NUMBER
SPT5420SIM
TEMPERATURE RANGE
–40 to +85 °C
PACKAGE
44L MQFP
SPT5420
8
6/26/01
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