ST10F166 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'ST10F166' PDF : 62 Pages View PDF
ST10F166
7 CENTRAL PROCESSING UNIT (CPU)
The main core of the CPU consists of a 4-stage instruction pipeline, a 16-bit arithme-
tic and logic unit (ALU) and dedicated SFRs. Additional hardware provide a separate
multiply and divide unit, a bit-mask generator and a barrel shifter.
Based on these hardware provisions, most of the ST10F166 instructions can be exe-
cuted in just one machine cycle which requires 100 ns at 20 MHz CPU clock. For ex-
ample, shift and rotate instructions are always processed during one machine cycle
independent of the number of bits to be shifted. For fast execution: All multiple-cycle
instructions have been optimized . A 32-/16 bit division in 1 µs, a 16 × 16 bit multipli-
cation in 0.5 µs, and program branches in 200 ns. Another pipeline optimization, the
’Jump Cache’, allows reducing the execution time of repeatedly performed jumps in a
loop from 200 ns to 100 ns.
The CPU disposes of an actual register context consisting of up to 16 wordwide
GPRs which are physically allocated within the on-chip RAM area. A Context Pointer
(CP) register determines the base address of the active register bank to be accessed
by the CPU at the time. The number of register banks is only restricted by the availa-
ble internal RAM space. For easy parameter passing, register banks can also be or-
ganized to overlapping.
A system stack of up to 512 bytes is provided as a storage for temporary data. The
system stack is allocated in the on-chip RAM area, and it is accessed by the CPU via
the stack pointer (SP) register. Two separate SFRs, STKOV and STKUN, are implic-
itly compared against the stack pointer value upon each stack access for the detec-
tion of a stack overflow or underflow.
15/62
Share Link: 
