ST10F166 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'ST10F166' PDF : 62 Pages View PDF
ST10F166
Interrupt System (Cont’d)
Except when another higher prioritized trap service being in progress, a hardware
trap will interrupt any actual program execution. In turn, hardware trap services can
normally not be interrupted by standard or PEC interrupts.
The following table shows all of the possible exceptions or error conditions that can
arise during run-time:
Table 4. Exceptions and Errors during Runtime
Exception Condition
Reset Functions:
Hardware Reset
Software Reset
Watchdog Timer Overflow
Trap
Flag
Trap
Vector
RESET
RESET
RESET
Vector
Location
0h
0h
0h
Class A Hardware Traps:
Non-Maskable Interrupt
Stack Overflow
Stack Underflow
NMI
STKOF
STKUF
Class B Hardware Traps:
Undefined Opcode
Protected Instruction Fault
Illegal Word Operand Access
Illegal Instruction Access
Illegal External Bus Access
Reserved
UNDOPC
PRTFLT
ILLOPA
ILLINA
ILLBUS
NMITRAP
08h
STOP-
TRAP
10h
STUTRAP
18h
BTRAP
BTRAP
BTRAP
BTRAP
BTRAP
28h
28h
28h
28h
28h
[2Ch - 3Ch]
Trap
Number
0h
0h
0h
2h
4h
6h
Ah
Ah
Ah
Ah
Ah
[Bh - Fh]
Trap
priority
III
III
III
II
II
II
I
I
I
I
I
Software Traps
TRAP Instruction
Any
[0h - 1FCh]
in steps
of 4h
Any
[0h - 7Fh]
Current
CPU Pri-
ority
19/62
Share Link: 
