ST10F166 View Datasheet(PDF) - STMicroelectronics
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MFG CO.
'ST10F166' PDF : 62 Pages View PDF
ST10F166
8 INTERRUPT SYSTEM
With an interrupt response time within a range from 250 ns to 500 ns (in case of inter-
nal program execution), the ST10F166 is capable of reacting very fast to the occur-
ance of non-deterministic events.
The architecture of the ST10F166 supports several mechanisms for fast and flexible
response to service requests that can be generated from various sources internal or
external to the microcontroller. Any of these interrupt requests can be programmed to
being serviced by the Interrupt Controller or by the Peripheral Event Controller (PEC).
In contrast to a standard interrupt service where the current program execution is
suspended and a branch to the interrupt vector table is performed, just one cycle is
’stolen’ from the current CPU activity to perform a PEC service. A PEC service im-
plies a single byte or word data transfer between any two memory locations with an
optional increment of either the PEC source or the destination pointer. An individual
PEC transfer counter is implicitly decremented for each PEC service except when op-
erating in the continuous transfer mode. When this counter reaches zero, a standard
interrupt is performed to the corres-ponding source related vector location.
PEC services are very well suited, for example, for supporting the transmission or re-
ception of blocks of data, or for transferring A/D converted results to a memory table.
The ST10F166 has 8 PEC chan-nels each of which offers such fast interrupt-driven
data transfer capabilities.
A separate control register which contains an interrupt request flag, an interrupt ena-
ble flag and an interrupt priority bit field exists for each of the possible interrupt sourc-
es. Via its related register, each source can be programmed to one of sixteen inter-
rupt priority levels. Once having been accepted by the CPU, an interrupt service can
only be interrupted by a higher prioritized service request. For the standard interrupt
processing, each of the possible interrupt sources has a dedicated vector location.
Software interrupts are supported by means of the ’TRAP’ instruction in combination
with an individual trap (interrupt) number.
The ST10F166 also provides an efficient mechanism to identify and to process ’Hard-
wareTraps’ exceptions or error conditions that arise during run-time. Hardware traps
cause immediate non-maskable system reaction which is similar to a standard inter-
rupt service (branching to a dedicated vector table location).
The occurrence of a hardware trap is additionally signified by an individual bit in the
trap flag register (TFR).
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