ST10F168-Q3 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'ST10F168-Q3' PDF : 74 Pages View PDF
ST10F168
17.2 - Synchronous Reset (Warm Reset)
A synchronous reset is triggered when RSTIN pin
is pulled low while VPP pin is at high level. In order
to properly activate the internal reset logic of the
MCU, the RSTIN pin must be held low, at least,
during 4 TCL (2 periods of CPU clock). The I/O
pins are set to high impedance and RSTOUT pin is
driven low. After RSTIN level is detected, a short
duration of 12 TCL (approximately 6 periods of
CPU clock) elapes, during which pending internal
hold states are cancelled and the current internal
access cycle if any is completed. External bus
cycle is aborted. The internal pulldown of RSTIN
pin is activated if bit BDRSTEN of SYSCON reg-
ister was previously set by software. This bit is
always cleared on power-on or after a reset
sequence.
Exit of Synchrounous Reset State
The internal reset sequence starts for 1024 TCL
(512 periods of CPU clock) and RSTIN pin level is
sampled. The reset sequence is extended until
RSTIN level becomes high. Then, the MCU
restarts. The system configuration is latched from
Port0 and ALE, RD and R/W pins are driven to
their inactive level. The MCU starts program exe-
cution from memory location 00'0000h in code
segment 0. This starting location will typically
point to the general initialization routine. Timing of
synchronous reset sequence are summarized in
Figure 10 and 11.
Figure 10 : Synchronous Warm Reset: Short low pulse on RSTIN
4 TCL 12 TCL
min. max.
1024 TCL
6 or 8 TCL3
CPU Clock
RSTIN
VPP
RSTOUT
ALE
1
200µA Discharge
Internally pulled low4
2 VPP > 2.5V Asynchronous Reset not entered.
Port0
Internal
Reset
Signal
Reset Configuration
Latching point of Port0
for system start-up configuration
INST #1
Notes: 1. RSTIN assertion can be released there.
2. If during the reset condition (RSTIN low), Vpp voltage drops below the threshold voltage (about 2.5V for 5V operation), the
asynchronous reset is then immediately entered.
3. RSTIN rising edge to internal latch of Port0 is 3CPU clock cycles (6 TCL) if the PLL is bypassed and the prescaler is on
(fCPU = fXTAL / 2), else it is 4 CPU clock cycles (8 TCL).
4) RSTIN pin is pulled low if bit BDRSTEN (bit 5 of SUSCON register) was previously set by software. Bit BDRSTEN is cleared after
reset.
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