ST10F168
The simplest way to reset the ST10F168 is to
insert a capacitor C1 between RSTIN pin and VSS,
and a capacitor between VPP pin and VSS (C0)
with a pullup resistor R0 between VPP pin and
VCC. The input RSTIN provides an internal pullup
device equalling a resistor of 50kΩ to 150kΩ (the
minimum reset time must be determined by the
lowest value). Select C1 that produce a sufficient
discharge time to permit the internal or external
oscillator and / or internal PLL to stabilize.
To insure correct power-up reset with controlled
supply current consumption, specially if clock sig-
nal requires a long period of time to stabilized, an
asynchronous hardware reset is required during
power-up. It is recommended to connect the exter-
nal R0C0 circuit shown in Figure 12 to the VPP
pin. On power-up, the logical low level on VPP pin
forces an asynchronous harware reset when
RSTIN is asserted.
The external pullup R0 will then charge the capac-
itor C0. Note that an internal pulldown device on
VPP pin is turned on when RSTIN pin is low, and
causes the external capacitor (C0) to begin dis-
charging at a typical rate of 100µA to 200µA. With
this mechanism, after power-up reset, short low
pulses applied on RSTIN produce synchronous
hardware reset. If RSTIN is asserted longer than
Figure 13 : Internal (simplified) Reset Circuitry
EINIT Instruction
Clr
Q
Set
Reset State
Machine
Clock
the time needed for C0 to be discharged by the
internal pulldown device, then the device is forced
in an asynchronous reset. This mechanism
insures recovery from very catastrophic failure.
Figure 12 : Minimum External Reset Circuitry
RSTOUT
External Hardware
RSTIN
+
C1
a) Hardware
Reset
VCC
R0
VPP
ST10F168
+
C0
b) For Power-up
Reset
(and Interruptible
Power-down
mode)
RSTOUT
VCC
Internal
Reset
Signal
Trigger
SRST instruction
watchdog overflow
Clr
Reset Sequence BDRSTEN
(512 CPU Clock Cycles)
RSTIN
Asynchronous
Reset
VPP (Flash device)
From/to Exit
Powerdown
Circuit
VCC
VPP
Weak Pulldown
(~200µA)
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