ST10F269Z2QX View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'ST10F269Z2QX' PDF : 161 Pages View PDF
ST10F269Z2Qx
6 - CENTRAL PROCESSING UNIT (CPU)
The CPU includes a 4-stage instruction pipeline, a
16-bit arithmetic and logic unit (ALU) and dedi-
cated SFRs. Additional hardware has been added
for a separate multiply and divide unit, a bit-mask
generator and a barrel shifter.
Most of the ST10F269Z2Qx’s instructions can be
executed in one instruction cycle which requires
50ns at 40MHz CPU clock. For example, shift and
rotate instructions are processed in one instruc-
tion cycle independent of the number of bits to be
shifted.
Multiple-cycle instructions have been optimized:
branches are carried out in 2 cycles, 16 x 16-bit
multiplication in 5 cycles and a 32/16-bit division
in 10 cycles.
The jump cache reduces the execution time of
repeatedly performed jumps in a loop, from
2 cycles to 1 cycle.
The CPU uses a bank of 16 word registers to run
the current context. This bank of General Purpose
Registers (GPR) is physically stored within the
on-chip Internal RAM (IRAM) area. A Context
Pointer (CP) register determines the base
address of the active register bank to be accessed
by the CPU.
The number of register banks is only restricted by
the available Internal RAM space. For easy
parameter passing, a register bank may overlap
others.
A system stack of up to 1024 bytes is provided as
a storage for temporary data. The system stack is
allocated in the on-chip RAM area, and it is
accessed by the CPU via the stack pointer (SP)
register.
Two separate SFRs, STKOV and STKUN, are
implicitly compared against the stack pointer
value upon each stack access for the detection of
a stack overflow or underflow.
Figure 9 : CPU Block Diagram (MAC Unit not included)
256K Byte
Flash
memory
32
SP
STKOV
STKUN
Exec. Unit
Instr. Ptr
4-Stage
Pipeline
PSW
SYSCON
BUSCON 0
BUSCON 1
BUSCON 2
BUSCON 3
BUSCON 4
Data Pg. Ptrs
CPU
MDH
MDL
Mul./Div.-HW
Bit-Mask Gen.
ALU
16-Bit
Barrel-Shift
CP
ADDRSEL 1
ADDRSEL 2
ADDRSEL 3
ADDRSEL 4
Code Seg. Ptr.
R15
General
Purpose
Registers
R0
16
2K Byte
Internal
RAM
Bank
n
Bank
i
Bank
16
0
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