ST10F269Z2QX View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'ST10F269Z2QX' PDF : 161 Pages View PDF
ST10F269Z2Qx
Table 4 : Instruction Set Summary
Mnemonic
Description
JNBS
Jump relative and set bit if direct bit is not set
CALLA, CALLI, CALLR Call absolute/indirect/relative subroutine if condition is met
CALLS
Call absolute subroutine in any code segment
PCALL
Push direct word register onto system stack and call absolute subroutine
TRAP
Call interrupt service routine via immediate trap number
PUSH, POP
Push/pop direct word register onto/from system stack
SCXT
Push direct word register onto system stack and update register with word
operand
RET
Return from intra-segment subroutine
RETS
Return from inter-segment subroutine
RETP
Return from intra-segment subroutine and pop direct
word register from system stack
RETI
Return from interrupt service subroutine
SRST
Software Reset
IDLE
Enter Idle Mode
PWRDN
Enter Power Down Mode (supposes NMI-pin being low)
SRVWDT
Service Watchdog Timer
DISWDT
Disable Watchdog Timer
EINIT
Signify End-of-Initialization on RSTOUT-pin
ATOMIC
Begin ATOMIC sequence
EXTR
Begin EXTended Register sequence
EXTP(R)
Begin EXTended Page (and Register) sequence
EXTS(R)
Begin EXTended Segment (and Register) sequence
NOP
Null operation
Bytes
4
4
4
4
2
2
4
2
2
2
2
4
4
4
4
4
4
2
2
2/4
2/4
2
6.3 - MAC Coprocessor Specific Instructions
The following table gives an overview of the MAC
instruction set. All the mnemonics are listed with
the addressing modes that can be used with each
instruction.
For each combination of mnemonic and address-
ing mode this table indicates if it is repeatable or
not.
New addressing capabilities enable the CPU to
supply the MAC with up to 2 operands per instruc-
tion cycle. MAC instructions: multiply, multi-
ply-accumulate, 32-bit signed arithmetic operations
and the CoMOV transfer instruction have been
added to the standard instruction set. Full details
are provided in the ‘ST10 Family Programming
Manual’. Double indirect addressing requires two
pointers. Any GPR can be used for one pointer, the
other pointer is provided by one of two specific
SFRs IDX0 and IDX1. Two pairs of offset registers
QR0/QR1 and QX0/QX1 are associated with each
pointer (GPR or IDXi).
The GPR pointer allows access to the entire
memory space, but IDXi are limited to the internal
Dual-Port RAM, except for the CoMOV instruc-
tion.
38/161
Share Link: 
