ST10F269Z2QX View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'ST10F269Z2QX' PDF : 161 Pages View PDF
ST10F269Z2Qx
6.1.1 - Features
6.1.1.1 - Enhanced Addressing Capabilities
– New addressing modes including a double indi-
rect addressing mode with pointer post-modifi-
cation.
– Parallel Data Move: this mechanism allows one
operand move during Multiply-Accumulate in-
structions without penalty.
– New transfer instructions CoSTORE (for fast ac-
cess to the MAC SFRs) and CoMOV (for fast
memory to memory table transfer).
6.1.1.2 - Multiply-Accumulate Unit
– One-cycle execution for all MAC operations.
Figure 10 : MAC Unit Architecture
– 16 x 16-bit signed/unsigned parallel multiplier.
– 40-bit signed arithmetic unit with automatic sat-
uration mode.
– 40-bit accumulator.
– 8-bit left/right shifter.
– Full instruction set with multiply and multiply-ac-
cumulate, 32-bit signed arithmetic and compare
instructions.
6.1.1.3 - Program Control
– Repeat Unit: allows some MAC co-processor in-
structions to be repeated up to 8192 times. Re-
peated instructions may be interrupted.
– MAC interrupt (Class B Trap) on MAC condition
flags.
GPR Pointers *
Operand 1
Operand 2
16 16
IDX0 Pointer
IDX1 Pointer
QR0 GPR Offset Register
QR1 GPR Offset Register
QX0 IDX Offset Register
QX1 IDX Offset Register
Interrupt
Controller
ST10 CPU
MRW
Repeat Unit
MCW
Concatenation
16 x 16
signed/unsigned
Multiplier
32
32
Mux
Sign Extend
Scaler
0h
08000h
40 40 40
Mux
0h
40
40
Mux
40
40
A
B
40-bit Signed Arithmetic Unit
Control Unit
MSW
Flags MAE
40
MAH
MAL
40
8-bit Left/Right
Shifter
Note: * Shared with standard ALU.
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