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REV. 5.0.0
ST16C650A
2.90V TO 5.5V UART WITH 32-BYTE FIFO
FIGURE 18. DATA BUS READ TIMING IN INTEL BUS MODE WITH AS# TIED TO GND
A0-
A2
CS2#
CS0
CS1
IOR#
IOR
D0-D7
TAS
TRDV
Valid
Address
TCS
TRD
Valid
Data
TAH
TAS
TDY
TDD
TRDV
Valid
Address
TCS
TRD
Valid
Data
TAH
TDD
Note: Only one chipselect and one read strobe should be used.
FIGURE 19. DATA BUS WRITE TIMING IN INTEL BUS MODE WITH AS# TIED TO GND
A0-
A2
CS2#
CS1
CS0
IOW#
IOW
D0-D7
Valid
Address
TAS
TCS
TWR
TDS1
Valid
Data
TAH
TAS
TDY
TDH1
Valid
Address
TCS
TWR
TDS1
Valid
Data
TAH
TDH1
Note: Only one chipselect and one write strobe should be used.
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