ST16C650A
2.90V TO 5.5V UART WITH 32-BYTE FIFO
FIGURE 20. DATA BUS READ TIMING IN INTEL BUS MODE USING AS#
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REV. 5.0.0
AS#
TAS1
A0-A2
CS2#
TCS1
CS0 or CS1
IOR#
IOR
DDIS#
TASW
TAH1
Valid
Address
TCS
TCSH
TRD1
TRD
TDIS
D0-D7
TRDV
Valid
Data
TAS2
TCS2
TDY
TASW
TAH2
Valid
Address
TCS
TCSH
TRD2
TRD
TDIS
TDD
TRDV
TDD
Valid
Data
Note: Only one chipselect and one read strobe should be used.
FIGURE 21. DATA BUS WRITE TIMING IN INTEL BUS MODE USING AS#
AS#
TAS1
A0-A2
TCS1
CS2#
CS0 or CS1
IOW#
IOW
D0-D7
TASW
TAH1
Valid
Address
TCS
TCSH
TWR1
TWR
TDS2
Valid
Data
TAS2
TCS1
TDY
TDH2
Note: Only one chipselect and one write strobe should be used.
TASW
TAH2
Valid
Address
TCS
TCSH
TWR1
TWR
TDS2
Valid
Data
TDH2
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