ST16C650AIQ48 View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'ST16C650AIQ48' PDF : 52 Pages View PDF
ST16C650A
2.90V TO 5.5V UART WITH 32-BYTE FIFO
FIGURE 28. TRANSMIT READY & INTERRUPT TIMING [FIFO MODE, DMA MODE DISABLED]
TX FIFO
Empty
TX
(Unloading)
INT*
IER[1]
enabled
TXRDY#
Data in
TX FIFO
Start
Bit
Stop
Bit
S D0:D7 T
ISR is read
S D0:D7 T S D0:D7 T T S D0:D7 T S D0:D7 T
TSI
ISR is read
TX FIFO fills up
to trigger level
TWRI
TX FIFO drops
below trigger level
TWT
IOW#
(Loading data
into FIFO)
*INT is cleared when the ISR is read or when TX FIFO fills up to the trigger level.
áç
REV. 5.0.0
Last Data Byte
Transmitted
S D0:D7 T
TSRT
TX FIFO
Empty
TXDMA#
FIGURE 29. TRANSMIT READY & INTERRUPT TIMING [FIFO MODE, DMA MODE ENABLED]
Start
Bit
Stop
Bit
TX
(Unloading)
S D0:D7 T S D0:D7 T
IER[1]
enabled
ISR Read
D0:D7 S D0:D7 T
S D0:D7 T S D0:D7 T
TSRT
TSI
Last Data Byte
Transmitted
S D0:D7 T
ISR Read
INT*
TXRDY#
TX FIFO fills up
to trigger level
TWRI
TX FIFO
Full
TX FIFO drops
below trigger level
At least 1
empty location
in FIFO
TWT
IOW#
(Loading data
into FIFO)
*INT cleared when the ISR is read or when TX FIFO fills up to trigger level.
TXDMA
48
Share Link: 
