ST18-AU1 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'ST18-AU1' PDF : 87 Pages View PDF
ST18-AU1
HTIEN
STOPIEN
ACKFIEN
BERRIEN
-
Transfer interrupt enable
0
transfer interrupt disabled
1
transfer interrupt enabled
Stop interrupt enable
0
stop interrupt disabled
1
stop interrupt enabled
Acknowledge fail interrupt
0
acknowledge fail interrupt disabled
1
acknowledge fail interrupt enabled
Bus error interrupt
0
bus error interrupt disabled
1
bus error interrupt enabled
RESERVED, read as 0.
HSR: Host status register
All bits are reset when the register is read. The register can only be read by the D950.
15 14 13 12
11
10
9
8
765432 1
0
- - - BERR ACK- STOP HDRR HDRW - - - - - - DAT- BUSY
FAIL
RQ RQ
ADIR
Bit
BUSY
DATADIR
HDRWRQ
HDRRRQ
STOP
ACKFAIL
BERR
-
Function
Set when Valid slave address detected, until Stop event or Restart event with invalid slave
address.
Data direction (valid when Busy bit is set).
0
receive data from host
1’
send data to host
HDR write request. Set when data is required by the host. Data needs to be written into
the HDR register, this is reset when the HSR register is read.
Host read request. Set when data has been sent by the host. Data needs to be read from
the HDR register, this is reset when the HSR register is read.
Stop. Set when a stop condition is detected.
Acknowledge fail. Set when the host does not generate an acknowledge after one data
byte has been sent.
Bus error. Set when a misplaced start or stop condition is detected during transmission.
RESERVED, read as 0.
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