ST18D952 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'ST18D952' PDF : 67 Pages View PDF
ST18952
STDR: SIO Transmit data register
(SIO0 address = 0060h reset value = 0000h, write only)
(SIO1 address = 00E0h reset value = 0000h, write only)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
STD STD STD STD STD STD STD STD STD STD STD STD STD STD STD STD
15 14 13 12 11 10 9
8
7
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5
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2
1
0
Bit
STD(15:0)
Function
SIO Transmit data (STD(15) = msb)
• STD contains the data to be transferred to the Transmit Shift register at the beginning
of the next sub-frame or time slot. The data is transmitted msb first.
• When 8-bit data format (SCR/SWL = ‘1’) is used, the byte must be left justified (written
on bits 7 to 0, bits 15 to 8 are ignored). The msb is bit 7.
SRDR: SIO Receive data register
(SIO0 address = 0061h, reset value = xxxxh, read only)
(SIO1 address = 00E1h, reset value = xxxxh, read only)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SRD SRD SRD SRD SRD SRD SRD SRD SRD SRD SRD SRD SRD SRD SRD SRD
15 14 13 12 11 10 9
8
7
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5
4
3
2
1
0
Bit
SRD(15:0)
Function
SIO Receive data (SRD(15) = msb)
• SRD contains the data transferred from the Receive Shift register at the end of the
last sub-frame or time slot. The data is right justified (msb = bit 15).
• When 8-bit data format (SCR/SWL = ‘1’) is used, the byte is left justified (significative
on bits 7 to 0, bits 15 to 8 are ignored). The msb is bit 7.
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