ST18D952 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'ST18D952' PDF : 67 Pages View PDF
ST18952
the D950 parallel port (input or output), the interrupt controller can be fed by the D950 parallel
port output.
INTR: Interrupt vector register
(Address = 004Ah, Reset = 0000h, Write only)
In the case of the interrupt controller being inhibited (bit 8 of the PICR register set to ‘1’), the
INTR register controls interrupt vector generation. This register must be initialized (INTR=0000
after reset) and can not be read.
After reset, ITC inputs are fed with external interrupt requests.
DMAR: DMA management register
The DMA controller DMARQ0-3 inputs and DMACK0-3 outputs are available as primary
inputs, in case of SIO inhibition. This is set by the system register DMAR.
(Address: 004Bh, Reset = 0000h, Read/Write):
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Not used
D3 D2 D1 D0
Bit
D0
D1
D2
D3
Bit 4 - 15
Function
0: DMARQ0 connected to DMARQ0 SIO0 and DMACK0 connected to DMACK0 SIO0
1: DMARQ0 connected to external DMARQ0 input called (DMARQ0_SRD0)
and DMACK0 connected to external DMACK0 input called (DMACK0_STD0)
0: DMARQ1 connected to DMARQ1 SIO0 and DMACK1 connected to DMACK1 SIO0
1: DMARQ1 connected to external DMARQ1 input called (DMARQ1_SCK0)
and DMACK1 connected to external DMACK1 input called (DMACK1_SFS0)
0: DMARQ2 connected to DMARQ0 SIO1 and DMACK2 connected to DMACK0 SIO1
1: DMARQ2 connected to external DMARQ2 input called (DMARQ2_SRD1)
and DMACK2 connected to external DMACK2 input called (DMACK2_STD1)
0: DMARQ3 connected to DMARQ1 SIO1 and DMACK3 connected to DMACK1 SIO1
1: DMARQ3 connected to external DMARQ3 input called (DMARQ3_SCK1)
and DMACK3 connected to external DMACK3 input called (DMACK3_SFS1)
Not used
Outputs DIT0-3 are connected to the interrupt controller inputs ITRQ0-3 (via PICR system
register described above).
HOLD DMA output is connected to HOLD D950 input through an arbitration module, which
takes into account external HOLD requests and manages HOLDACK generation to the right
HOLD sender.
After reset, DMA requests come from the SIO.
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