ST6285B View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'ST6285B' PDF : 78 Pages View PDF
ST62T85B/E85B
4.5 A/D CONVERTER (ADC)
The A/D converter peripheral is an 8-bit analog to sion to allow stabilisation of the A/D converter.
digital converter with analog inputs as alternate I/O This action is also needed before entering WAIT
functions (the number of which is device depend- mode, since the A/D comparator is not automati-
ent), offering 8-bit resolution with a typical conver- cally disabled in WAIT mode.
sion time of 70us (at an oscillator clock frequency
of 8MHz).
During Reset, any conversion in progress is
stopped, the control register is reset to 40h and the
The ADC converts the input voltage by a process ADC interrupt is masked (EAI=0).
of successive approximations, using a clock fre-
quency derived from the oscillator with a division Figure 27. ADC Block Diagram
factor of twelve. With an oscillator clock frequency
less than 1.2MHz, conversion accuracy is de-
creased.
INTERRUPT
Selection of the input pin is done by configuring
CLOCK
Ain
CONVERTER
RESET
the related I/O line as an analog input via the Op-
AVSS
tion and Data registers (refer to I/O ports descrip-
AVDD
tion for additional information). Only one I/O line
must be configured as an analog input at any time.
) The user must avoid any situation in which more
t(s than one I/O pin is selected as an analog input si-
c multaneously, to avoid device malfunction.
u The ADC uses two registers in the data space: the
d ADC data conversion register, ADR, which stores
ro the conversion result, and the ADC control regis-
P ter, ADCR, used to program the ADC functions.
te A conversion is started by writing a “1” to the Start
bit (STA) in the ADC control register. This auto-
le matically clears (resets to “0”) the End Of Conver-
o sion Bit (EOC). When a conversion is complete,
s the EOC bit is automatically set to “1”, in order to
b flag that conversion is complete and that the data
O in the ADC data conversion register is valid. Each
- conversion has to be separately initiated by writing
) to the STA bit.
t(s The STA bit is continuously scanned so that, if the
c user sets it to “1” while a previous conversion is in
u progress, a new conversion is started before com-
d pleting the previous one. The start bit (STA) is a
ro write only bit, any attempt to read it will show a log-
ical “0”.
P The A/D converter features a maskable interrupt
te associated with the end of conversion. This inter-
le rupt is associated with interrupt vector #4 and oc-
o curs when the EOC bit is set (i.e. when a conver-
s sion is completed). The interrupt is masked using
Obthe EAI (interrupt mask) bit in the control register.
CONTROL REGISTER RESULT REGISTER
8
CORE
CONTROL SIGNALS
8
CORE
VA00418
4.5.1 Application Notes
The A/D converter does not feature a sample and
hold circuit. The analog voltage to be measured
should therefore be stable during the entire con-
version cycle. Voltage variation should not exceed
±1/2 LSB for the optimum conversion accuracy. A
low pass filter may be used at the analog input
pins to reduce input voltage variation during con-
version.
When selected as an analog channel, the input pin
is internally connected to a capacitor Cad of typi-
cally 12pF. For maximum accuracy, this capacitor
must be fully charged at the beginning of conver-
sion. In the worst case, conversion starts one in-
struction (6.5 µs) after the channel has been se-
lected. In worst case conditions, the impedance,
ASI, of the analog voltage source is calculated us-
ing the following formula:
6.5µs = 9 x Cad x ASI
(capacitor charged to over 99.9%), i.e. 30 kΩ in-
The power consumption of the device can be re-
duced by turning off the ADC peripheral. This is
cluding a 50% guardband. ASI can be higher if Cad
has been charged for a longer period by adding in-
done by setting the PDS bit in the ADC control reg- structions before the start of conversion (adding
ister to “0”. If PDS=“1”, the A/D is powered and en- more than 26 CPU cycles is pointless).
abled for conversion. This bit must be set at least
one instruction before the beginning of the conver-
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