ST6285B View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'ST6285B' PDF : 78 Pages View PDF
ST62T85B/E85B
4.6 SERIAL PERIPHERAL INTERFACE (SPI)
The on-chip SPI is an optimized serial synchro- operation Sout has to be programmed as open-
nous interface that supports a wide range of indus- drain output.
try standard SPI specifications. The on-chip SPI is
controlled by small and simple user software to
perform serial data exchange. The serial shift
clock can be implemented either by software (us-
ing the bit-set and bit-reset instructions), with the
on-chip Timer 1 by externally connecting the SPI
clock pin to the timer pin or by directly applying an
external clock to the Scl line.
The SCL, Sin and Sout SPI clock and data signals
are connected to 3 I/O lines on the same external
pins. With these 3 lines, the SPI can operate in the
following operating modes: Software SPI, S-BUS,
I²C-bus and as a standard serial I/O (clock, data,
enable). An interrupt request can be generated af-
ter eight clock pulses. Figure 28 shows the SPI
block diagram.
The peripheral is composed by an 8-bit Data/shift The SCL line clocks, on the falling edge, the shift
Register and a 4-bit binary counter while the Sin register and the counter. To allow SPI operation in
pin is the serial shift input and Sout is the serial slave mode, the SCL pin must be programmed as
shift output. These two lines can be tied together input and an external clock must be supplied to
to implement two wires protocols (I²C-bus, etc). this pin to drive the SPI peripheral.
When data is serialized, the MSB is the first bit. Sin
has to be programmed as input. For serial output
ct(s) Figure 28. SPI Block Diagram
In master mode, SCL is programmed as output, a
clock signal must be generated by software to set
and reset the port line.
te Produ CLK
bsole SCL
I/O Port
O Data Reg
- Direction
t(s) DIN
roduc Sin
I/O Port
P Data Reg
Obsolete Direction
SPI Interrupt Disable Register
Write
SPI Data Register
Read
RESET
RESET
Q4
CP
4-Bit Counter
Q4
(Q4=High after Clock8)
8-Bit Data
CP
Shift Register
DIN
Reset
Load
DOUT
Output
Set Res
Interrupt
Sout
I/O Port
OPR Reg.
0
8-Bit Tristate Data I/O
Enable
DOUT
D0............................D7
1 Data Reg
Direction
to Processor Data Bus
VR01504
53/78
53
Share Link: 
