ST6391 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'ST6391' PDF : 68 Pages View PDF
ST6391,92,93,95,97,99
TIMERS (Continued)
Figure 34. Timer Status Control Registers
TSCR
Imer 1&2 Status Control Registers
DAh Timer 1, DCh Timer 2,
Read/ Write
D7 D6 D5 D4 D3 D2 D1 D0
* Only Available in TSCR1
PS0 = Prescaler Mux. Select
PS1 = Prescaler Mux. Select
PS2 = Prescaler Mux. Select
PSI = Prescaler Initialize Bit
D4 = Timers Enable Bit*
D5 = Timers Enable Bit*
ETI = Enable Timer Inte rrupt
TMZ = Timer Zero Bit
TMZ. Low-to-high transition indicates that the timer
count register has decrement to zero. This bit must
be cleared by user software before to start with a
new count.
ETI. This bit, when set, enables the timer interrupt
(vector #3 for Timer 1, vector #1 for Timer 2) request.
If ETI=0 the timer interrupt is disabled. If ETI= 1 and
TMZ= 1 an interrupt request is generated.
D5. This is the timers enable bit D5. It must be
cleared to 0 together with a set to 1 of bit D4 to en-
able both Timer 1 and Timer 2 functions. It is not
implemented on TSCR2 register.
D4. This is the timers enable bit D4. This bit must
be set to 1 together with a clear to 0 of bit D5 to en-
able both Timer 1 and Timer 2 functions. It is not
implemented on TSCR2 register.
D5
D4
Timers
0
0
Disabled
0
1
Enabled
1
X
Reserved
PS1. Used to initialize the prescaler and inhibit its
countingwhile PSI = 0 the prescaler is set to 7Fh and
the counter is inhibited. When PSI = 1 the prescaler
is enabled to count downwards. As long as PSI= 0
both counter and prescaler are not running.
PS2-PS0. These bits select the division ratio of the
prescaler register. (see Table 9)
The TSCR1 and TSCR2 registers are cleared on
reset. The correct D4-D5 combination must be
written in TSCR1 by user’s software to enable the
operation of Timer 1 and Timer 2.
Table 9. Prescaler Division Factors
PS2
PS1
PS0
Divided By
0
0
0
1
0
0
1
2
0
1
0
4
0
1
1
8
1
0
0
16
1
0
1
32
1
1
0
64
1
1
1
128
Figure 35. Timer Counter Registers
TCR
Timer Counter 1&2 Register
D3h Timer 1, DBh Timer 2, Read/ Write
D7 D6 D5 D4 D3 D2 D1 D0
D7 - D0 = Counter bits
Figure 36. Timer Counter Registers
PSC
TimerPrescaler 1&2 Register
D2h Timer 1, DAh Timer 2, Read/ Write
D7 D6 D5 D4 D3 D2 D1 D0
D6 - D0 = Prescaler bits
Always read as “0”
30/64
®
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