ST6391 View Datasheet(PDF) - STMicroelectronics
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MFG CO.
'ST6391' PDF : 68 Pages View PDF
ST6391,92,93,95,97,99
SERIAL PERIPHERAL INTERFACE (Continued)
Start/Stop Acknowledge. The timing specs of the
S-BUS protocol require that data on the SDA (only
on this line for I2CBUS) and SEN lines be stable
during the “high” time of SCL. Two exceptions to
this rule are foreseen and they are used to signal
the start and stop condition of data transfer.
- On S-BUS by a transition of the SEN line (10
Start, 01 Stop) while the SCL line is at high
level.
- On I2CBUS by a transition of the SDA line (10
Start, 01 Stop) while the SCL line is at high
level.
Data are transmitted in 8-bit groups; after each
group, a ninth bit is interposed, with the purpose of
acknowledging the transmitting sequence (the
transmit device place a “1” on the bus, the acknow-
ledging receiver a “0”).
Interface Protocol. This paragraph deals with the
description of data protocol structure. The inter-
face protocol includes:
- A start condition
- A “slave chip address” byte, transmitted by the
master, containing two different information:
a. the code identifying the device the master
wants to address (this information is present in
the first seven bits)
b. the direction of transmission on the bus (this
information is given in the 8th bit of the byte);
“0” means “Write”, that is from the master to
the slave, while “1” means “Read”. The ad-
dressed slave must always acknowledge.
The sequence from, now on, is different according
to the value of R/W bit.
1. R/W = “0” (Write)
In all the following bytes the master acts as trans-
mitter; the sequence follows with:
a. an optional data byte to address (if needed) the
slave location to be written (it can be a word ad-
dress in a memory or a register address, etc.).
b. a “data” byte which will be written at the ad-
dress given in the previous byte.
c. further data bytes.
d. a STOP condition
A data transfer is always terminated by a stop con-
dition generated from the master. The ST639x pe-
ripheral must finish with a stop condition before
another start is given. Figure 44 shows an example
of write operation.
2. R/W = “1” (Read)
In this case the slave acts as transmitter and,
therefore, the transmission direction is changed. In
read mode two different conditions can be consid-
ered:
a. The master reads slave immediately after first
byte. In this case after the slave address sent
from the master with read condition enabled
the master transmitter becomes master re-
ceiver and the slave receiver becomes slave
transmitter.
b. The master reads a specified register or loca-
tion of the slave. In this case the first sent byte
will contain the slave address with write condi-
tion enabled, then the second byte will specify
the address of the register to be read. At this
moment a new start is given together with the
slave address in read mode and the procedure
will proceed as described in previous point “a”.
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