ST6391 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'ST6391' PDF : 68 Pages View PDF
ST6391,92,93,95,97,99
SERIAL PERIPHERAL INTERFACE (Continued)
Figure 49.Sofware Bus (Hardware Bus Disabled) Timing Diagram
STD SPI Protocol (Shift Register)
This protocol is similar to the I2CBUS with the ex-
ception that there is no acknowledge pulse and
there are no stop or start bits. The clock cannot be
slowed down by the externalperipherals.
In this case all three outputs should be high in or-
der not to lock the software I/Os from functioning.
SPI Standard Bus Protocol: The standard bus
protocol is selected by loading the SPI Control
Register 1 (SCR1 Add. EBh). Bit 0 named I2C must
be set at one and bit 1 named STD mut be reset.
When the standard bus protocol is selected bit 2 of
the SCR1 is meaningless.
This bit named STOP bit is used only in I2CBUS or
SBUS. However take care thet THE STOP BIT
MUST BE RESET WHEN THE STANDARD PRO-
TOCOL IS USED. This bit is set to ZERO after RE-
SET.
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