ST6391 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'ST6391' PDF : 68 Pages View PDF
ST6391,92,93,95,97,99
AFC A/D COMPARATOR (Continued)
Figure 53. AFC, IR and OSD Result Register
AFCR
AFC Result Register
(E4h, Read Only)
D7 D6 D5 D4 D3 D2 D1 D0
AD2-AD0 A/D = Conv Result
IR
VSYNC
Unused
D7-D5. These bits are not used.
VSYNC. This bit reads the status of the VSYNC
pin. It is inverted with respect to the pin.
IR. This bit reads the status of the IR latch. If a sig-
nal has been latched this bit will be high.
AD2-AD0. These bits store the real time conver-
sion of the value present on the AFC input pin. Un-
defined reset value.
Figure 54. Outputs Control Register
AFSR
AFC Shift Register
(E5h, Write Only)
D7 D6 D5 D4 D3 D2 D1 D0
Unused
A/D Shift Bit
Unused
D7, D6, D5, D4, D3, D1, D0. These bits are not
used.
A/D Shift. This bit determines the voltage range of
the AFC input. Writing a zero will select the 0.5V to
4.5V range. Writing a one will select the 1.0V to
5.0V range. Undefined after reset.
DEDICATED LATCHES
Two latches are available which may generate in-
terrupts to the ST639x core. The IR latch is set
either by the falling or rising edge of the signal on
pin PC6(IRIN). If bit 1 (IRPOSEDGE) of the latches
register (E9h) is high, then the latch will be trig-
gered on the rising edge of the signal at PC6(IRIN).
If bit 1 (IRPOSEDGE) is low, then the latch will be
triggered on the falling edge of the signal at
PC6(IRIN). The IR latch can be reset by setting bit
3 (RESIRLAT) of the latches register; the bit is set
only and a high should be written every time the IR
latch needs to be reset. If bit 2 (IRINTEN) of the
latches register (E9h) is high, then the output of the
IR latch, IRINTN, may generate an interrupt (#0).
IRINTN is inverted with respect to the state of the
IR latch. If bit 2 (IRINTEN) is low, then the output of
the IR latch, IRINTN, is forced high. The state of
the IR latch may be read from bit 3 (IRLATCH) of
register E4h; if the IR latch is set, then bit 3 will be
high. The PWR latch is set either by the falling or
rising edge of the signal on pin PC4(PWRIN). If bit
4 (PWREDGE) of the latches register (E9h) is high,
then the latch will be triggered on the rising edge of
the signal at PC4(PWRIN). If bit 4 (PWREDGE) is
low, then the latch will be triggered on the falling
edge of the signal at PC4(PWRIN). The PWR latch
can be reset by setting bit 6 (RESPWRLAT) of the
latches register; the bit is set only and a high
should be written every time the PWR latch needs
to be reset. If bit 5 (PWRINTEN) of the latches reg-
ister (E9h) is high, then the output of the PWR
latch, PWRINTN, may generate an interrupt (#4).
PWRINTN is inverted with respect to the state of
the PWR latch. If bit 5 (PWRINTEN) is low, then
the output of the PWR latch, PWRINTN, is forced
high.
42/64
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