ST72321BR9-AUTO View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
ST72321BR9-AUTO
STMicroelectronics
'ST72321BR9-AUTO' PDF : 247 Pages View PDF
ST72321Bxxx-Auto
Supply, reset and clock management
In the case of a drop in voltage, the AVD interrupt acts as an early warning, allowing
software to shut down safely before the LVD resets the microcontroller. See Figure 15.
The interrupt on the rising edge is used to inform the application that the VDD warning state
is over.
If the voltage rise time trv is less than 256 or 4096 CPU cycles (depending on the reset delay
selected by option byte), no AVD interrupt will be generated when VIT+(AVD) is reached.
If trv is greater than 256 or 4096 cycles
● two AVD interrupts will be received if the AVD interrupt is enabled before the VIT+(AVD)
threshold is reached: the first when the AVDIE bit is set, and the second when the
threshold is reached.
● only one AVD interrupt will occur if the AVD interrupt is enabled after the VIT+(AVD)
threshold is reached.
Figure 15. Using the AVD to monitor VDD (AVDS bit = 0)
VDD
VIT+(AVD)
Early Warning Interrupt
(Power has dropped, MCU not
not yet in reset)
Vhyst
VIT-(AVD)
VIT+(LVD)
VIT-(LVD)
trv VOLTAGE RISE TIME
AVDF bit
0
AVD INTERRUPT
REQUEST
IF AVDIE bit = 1
LVD RESET
1
RESET VALUE
INTERRUPT PROCESS
1
0
INTERRUPT PROCESS
Monitoring a voltage on the EVD pin
This mode is selected by setting the AVDS bit in the SICSR register.
The AVD circuitry can generate an interrupt when the AVDIE bit of the SICSR register is set.
This interrupt is generated on the rising and falling edges of the comparator output. This
means it is generated when either one of these two events occur:
● VEVD rises up to VIT+(EVD)
● VEVD falls down to VIT-(EVD)
The EVD function is illustrated in Figure 16.
For more details, refer to Chapter 19: Electrical characteristics.
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