Supply, reset and clock management
ST72321Bxxx-Auto
Figure 16. Using the voltage detector to monitor the EVD pin (AVDS bit = 1)
VEVD
VIT+(EVD)
VIT-(EVD)
Vhyst
AVDF
0
AVD INTERRUPT
REQUEST
IF AVDIE = 1
1
INTERRUPT PROCESS
0
INTERRUPT PROCESS
6.6.3
6.6.4
Low power modes
Table 10. Effect of low power modes on SI
Mode
Effect
Wait No effect on SI. AVD interrupts cause the device to exit from Wait mode.
Halt The SICSR register is frozen.
Interrupts
The AVD interrupt event generates an interrupt if the corresponding Enable Control Bit
(AVDIE) is set and the interrupt mask in the CC register is reset (RIM instruction).
Table 11. AVD interrupt control/wake-up capability
Interrupt event
Event flag Enable control bit Exit from Wait
AVD event
AVDF
AVDIE
Yes
Exit from Halt
No
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