ST72334J/N, ST72314J/N, ST72124J
SERIAL COMMUNICATIONS INTERFACE (Cont’d)
Figure 54. SCI Baud Rate and Extended Prescaler Block Diagram
EXTE NDED PRESCALER TRANSMITTE R RATE CONTROL
ETPR
EXTE NDED TRANS MITTER PRESCALE R REGISTER
ERPR
EXTE NDED RECEIVER PRESCALER REGISTER
fCPU
/16
EXTE NDED PRESCALER RECEIVER RATE CONTROL
EXTENDED PRESCALER
/2
/PR
TRANSMIT TER RATE
CONTR OL
BRR
SCP1SCP0SCT2 SCT1 SCT0 SCR2 SCR1SCR0
RECEIVER RATE
CONTROL
CONVENTIONAL BAUD RATE GENERATOR
TRANSMI TTER
CLOCK
RECE IVER
CLOCK
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