ST72T311R6T1 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

MFG CO.

ST72T311R6T1

8-BIT MCU WITH NESTED INTERRUPTS, EEPROM, ADC, 16-BIT TIMERS, 8-BIT PWM ART, SPI, SCI, CAN INTERFACES

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5.2 RESET SEQUENCE MANAGER (RSM)

5.2.1 Introduction

The reset sequence manager includes three RE-

SET sources as shown in Figure 12:

s External RESET source pulse

s Internal LVD RESET (Low Voltage Detection)

s Internal WATCHDOG RESET

These sources act on the RESET pin and it is al-

ways kept low during the delay phase.

The RESET service routine vector is fixed at ad-

dresses FFFEh-FFFFh in the ST7 memory map.

The basic RESET sequence consists of 3 phases

as shown in Figure 11:

s Delay depending on the RESET source

s 4096 CPU clock cycle delay

s RESET vector fetch

Figure 12. Reset Block Diagram

The 4096 CPU clock cycle delay allows the oscil-

lator to stabilise and ensures that recovery has

taken place from the Reset state.

The RESET vector fetch phase duration is 2 clock

cycles.

Figure 11. RESET Sequence Phases

DELAY

RESET

INTERNAL RESET

4096 CLOCK CYCLES

FETCH

VECTOR

RESET

VDD

RON

fCPU

INTERNAL

RESET

WATCHDOG RESET

LVD RESET

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