ST72T311R6T1 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

MFG CO.

ST72T311R6T1

8-BIT MCU WITH NESTED INTERRUPTS, EEPROM, ADC, 16-BIT TIMERS, 8-BIT PWM ART, SPI, SCI, CAN INTERFACES

STMicroelectronics 

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INTERRUPTS (Cont’d)

6.3 INTERRUPTS AND LOW POWER MODES

All interrupts allow the processor to exit the WAIT

low power mode. On the contrary, only external

and other specified interrupts allow the processor

to exit the HALT modes (see column “Exit from

HALT” in “Interrupt Mapping” table). When several

pending interrupts are present while exiting HALT

mode, the first one serviced can only be an inter-

rupt with exit from HALT mode capability and it is

selected through the same decision process

shown in Figure 15

Note: If an interrupt, that is not able to Exit from

HALT mode, is pending with the highest priority

when exiting HALT mode, this interrupt is serviced

after the first one serviced.

6.4 CONCURRENT & NESTED MANAGEMENT

The following Figure 16 and Figure 17 show two

different interrupt management modes. The first is

called concurrent mode and does not allow an in-

terrupt to be interrupted, unlike the nested mode in

Figure 17 The interrupt hardware priority is given

in this order from the lowest to the highest: MAIN,

IT4, IT3, IT2, IT1, IT0, TLI. The software priority is

given for each interrupt.

Warning: A stack overflow may occur without no-

tifying the software of the failure.

Figure 16. Concurrent interrupt management

SOF TWA RE

PRIORITY

I1

I0

LEVEL

IT2

RI M

MAI N

11 / 10

TLI

IT0

IT1

IT1

IT3

IT4

MAIN

10

3

11

3

11

3

11

3

11

3

11

3

11

3/0

Figure 17. Nested interrupt management

IT1

IT2

TLI

IT0

RI M

MAI N

11 / 10

IT4

IT4

IT1

IT3

SOF TWA RE

PRIORITY

I1

I0

LEVEL

IT2

MAIN

10

3

11

3

11

2

00

1

01

3

11

3

11

3/0

30/164

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