ST72T311R6T1 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
ST72T311R6T1
STMicroelectronics
'ST72T311R6T1' PDF : 164 Pages View PDF
ST72311R, ST72511R, ST72512R, ST72532R
RESET SEQUENCE MANAGER (Cont’d)
5.2.2 Asynchronous External RESET pin
The RESET pin is both an input and an open-drain
output with integrated RON weak pull-up resistor.
This pull-up has no fixed value but varies in ac-
cordance with the input voltage. It can be pulled
low by external circuitry to reset the device. See
electrical characteristics section for more details.
A RESET signal originating from an external
source must have a duration of at least th(RSTL)in in
order to be recognized as shown in Figure 13. This
detection is asynchronous and therefore the MCU
can enter reset state even in HALT mode.
The RESET pin is an asynchronous signal which
plays a major role in EMS performance. In a noisy
environment, it is recommended to follow the
guidelines mentioned in the electrical characteris-
tics section.
Figure 13. RESET Sequences
VDD
5.2.3 Internal Low Voltage Detection RESET
Two different RESET sequences caused by the in-
ternal LVD circuitry can be distinguished:
s Power-On RESET
s Voltage Drop RESET
The device RESET pin acts as an output that is
pulled low when VDD<VIT+ (rising edge) or
VDD<VIT- (falling edge) as shown in Figure 13.
The LVD filters spikes on VDD larger than tg(VDD) to
avoid parasitic resets.
5.2.4 Internal Watchdog RESET
The RESET sequence generated by a internal
Watchdog counter overflow is shown in Figure 13.
Starting from the Watchdog counter underflow, the
device RESET pin acts as an output that is pulled
low during tw(RSTL)out.
CAUTION: this output signal as not enought ener-
gy to be used to drive external devices.
VIT+
VIT-
WATCHDOG
RESET
RUN
LVD
RESET
DELAY
RUN
SHORT EXT.
RESET
DELAY
RUN
RUN
DELAY
EXTERNAL
RESET
SOURCE
RESET PIN
WATCHDOG
RESET
th(RSTL)in
tw(RSTL)out
WATCHDOG UNDERFLOW
INTERNAL RESET (4096 TCPU)
FETCH VECTOR
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