ST7689-G4 View Datasheet(PDF) - Sitronix Technology Co., Ltd.
Part Name
Description
MFG CO.
ST7689-G4
Sitronix Technology Co., Ltd.
'ST7689-G4' PDF : 195 Pages View PDF
6.4. Microprocessor Interface
ST7689
Name
/RST
IF[3:1]
/CS
A0
RW_WR
E_RD
I/O
Description
I
Reset input pin. When RST is “L”, and initialization is executed.
Parallel / Serial data input select input
IF3 IF2 IF1
MPU interface type
H
H
H 80 series 16-bit parallel
H
H
L 80 series 8-bit parallel
H
L
H 68 series 16-bit parallel
H
L
L 68 series 8-bit parallel
I
L
H
H 8-bit serial (4 line)
L
H
L 9-bit serial (3 line)
Note:
1. When fixing IF2=H & IF1=L, IF3 can be defined as parallel/Serial selection pin.
IF3=H: Parallel interface (80 8-bit); IF3=L: Serial interface (3-line)
2. Refer to Table 1.for detail interface connection.
Chip select input pin.
I
Data / Instruction I/O is enabled only when /CS is "L". When chip select is non-active, D0 to D15
become high impedance.
Register select input pin
A0 = "H": D0 to D15 or SI are display data
I
A0 = "L": D0 to D15 or SI are control data
** In 3-line/4-line interface this pad will be used for SCL function
Read / Write execution control pin. (This pin is only used in parallel interface)
MPU type RW_WR
Description
Read / Write control input pin
6800-series
RW
RW = “H” : read
I
RW = “L” : write
Write enable clock input pin.
8080-series
/WR
The data on D0 to D15 are latched at the
rising edge of the /WR signal.
When in the serial interface, connect it to VDDI.
Read / Write execution control pin. (This pin is only used in parallel interface)
MPU Type
E_RD
Description
Read / Write control input pin
I
RW= “H”: If E is “H”, D0 to D15 are in an output status.
6800-series
E
RW = “L”: The data on D0 to D15 are latched at the
falling edge of the E signal.
Version 1.0
Page 25 of 195
2009/10
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