ST7FLITE02Y1B6 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
ST7FLITE02Y1B6
STMicroelectronics
'ST7FLITE02Y1B6' PDF : 124 Pages View PDF
ST7LITE0xY0, ST7LITESxY0
LITE TIMER (Cont’d)
Input Capture
The 8-bit input capture register is used to latch the
free-running upcounter after a rising or falling edge
is detected on the LTIC pin. When an input capture
occurs, the ICF bit is set and the LTICR register
contains the value of the free-running upcounter.
An interrupt is generated if the ICIE bit is set. The
ICF bit is cleared by reading the LTICR register.
The LTICR is a read only register and always con-
tains the data from the last input capture. Input
capture is inhibited if the ICF bit is set.
11.1.4 Low Power Modes
Mode
SLOW
WAIT
ACTIVE HALT
HALT
Description
No effect on Lite timer
(this peripheral is driven directly by
fOSC/32)
No effect on Lite timer
No effect on Lite timer
Lite timer stops counting
Figure 33. Input Capture Timing Diagram
fCPU
fOSC/32
4µs
(@ 8 MHz fOSC)
8-bit COUNTER 01h
02h
03h
04h
11.1.5 Interrupts
Interrupt
Event
Timebase
Event
IC Event
Event
Flag
TBF
ICF
Enable
Control
Bit
TBIE
ICIE
Exit
from
Wait
Exit
from
Halt
Exit
from
Active-
Halt
Yes
Yes No
No
Note: The TBF and ICF interrupt events are con-
nected to separate interrupt vectors (see Inter-
rupts chapter).
Timebase and IC events generate an interrupt if
the enable bit is set in the LTCSR register and the
interrupt mask in the CC register is reset (RIM in-
struction).
05h
06h
07h
CLEARED
BY S/W
READING
LTIC REGISTER
LTIC PIN
ICF FLAG
LTICR REGISTER
xxh
04h
07h
t
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