ST7FLITE29 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
ST7FLITE29
STMicroelectronics
'ST7FLITE29' PDF : 133 Pages View PDF
ST7LITE2
13.10 COMMUNICATION INTERFACE CHARACTERISTICS
13.10.1 SPI - Serial Peripheral Interface
Subject to general operating conditions for VDD,
fOSC, and TA unless otherwise specified.
Refer to I/O port characteristics for more details on
the input/output alternate function characteristics
(SS, SCK, MOSI, MISO).
Symbol
fSCK =
1/tc(SCK)
tr(SCK)
tf(SCK)
tsu(SS) 1)
th(SS) 1)
tw(SCKH)
tw(SCKL)
tsu(MI)
tsu(SI)
th(MI)
th(SI)
ta(SO)
tdis(SO)
tv(SO)
th(SO)
tv(MO)
th(MO)
Parameter
SPI clock frequency
SPI clock rise and fall time
SS setup time 4)
SS hold time
SCK high and low time
Data input setup time
Data input hold time
Data output access time
Data output disable time
Data output valid time
Data output hold time
Data output valid time
Data output hold time
Conditions
Master
fCPU=8MHz
Slave
fCPU=8MHz
Slave
Slave
Master
Slave
Master
Slave
Master
Slave
Slave
Slave
Slave (after enable edge)
Master (after enable edge)
Min
fCPU/128 =
0.0625
0
Max
fCPU/4 =
2
fCPU/2 =
4
see I/O port pin description
(4 x TCPU) +150
120
100
90
100
100
100
100
0
120
240
120
0
120
0
Unit
MHz
ns
Figure 86. SPI Slave Timing Diagram with CPHA=0 3)
SS INPUT
tsu(SS)
tc(SCK)
th(SS)
CPHA=0
CPOL=0
CPHA=0
CPOL=1
ta(SO)
MISO OUTPUT
see note 2
tsu(SI)
ttww((SSCCKKLH))
tv(SO)
MSB OUT
th(SI)
BIT6 OUT
th(SO)
tr(SCK)
tf(SCK)
LSB OUT
tdis(SO)
see
note 2
MOSI INPUT
MSB IN
BIT1 IN
LSB IN
Notes:
1. Data based on design simulation and/or characterisation results, not tested in production.
2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has
its alternate function capability released. In this case, the pin status depends on the I/O port configuration.
3. Measurement points are done at CMOS levels: 0.3xVDD and 0.7xVDD.
4. Depends on fCPU. For example, if fCPU = 8MHz, then TCPU = 1/ fCPU = 125ns and tSU(SS) = 550ns
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