ST7LUS5, ST7LU05, ST7LU09
Interrupts
Note:
Caution:
Use of LVD with capacitive power supply: If power cuts occur in the application with this type
of power supply, it is recommended to pull VDD down to 0V to ensure optimum restart
conditions. Refer to circuit example in Figure 67 and Note 4 on page 124.
The LVD is an optional function which can be selected by option byte (see Section 14.1 on
page 131). It allows the device to be used without any external reset circuitry. If the LVD is
disabled, an external circuitry must be used to ensure a proper power-on reset.
It is recommended to make sure that the VDD supply voltage rises monotonously when the
device is exiting from reset, to ensure the application functions properly.
If an LVD reset occurs after a watchdog reset has occurred, the LVD takes priority and
clears the watchdog flag.
Figure 15. Low voltage detector vs. reset
) VDD
ct(s VIT+(LVD)
u VIT-(LVD)
Vhys
te Prod ct(s) RESET
sole rodu Figure 16. Reset and supply management block diagram
Productt((ss)) -- OObbsolete P RESET
Watchdog
timer (WDG)
Status flag
Reset sequence
manager
(RSM)
System integrity management
SICSR
00
0
0
0
LVD
RF
0
0
7
0
solete roduc Low voltage
VSS
detector
OObbsolete PVDD
(LVD)
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