ST7FLU05MCE View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
ST7FLU05MCE
STMicroelectronics
'ST7FLU05MCE' PDF : 124 Pages View PDF
ST7LUS5, ST7LU05, ST7LU09
Power saving modes
As soon as halt mode is entered, and if the AWUEN bit has been set in the AWUCSR
register, the AWU RC oscillator provides a clock signal (fAWU_RC). Its frequency is divided by
a fixed divider and a programmable prescaler controlled by the AWUPR register. The output
of this prescaler provides the delay time. When the delay has elapsed, the following actions
are performed:
● The AWUF flag is set by hardware,
● an interrupt wakes up the MCU from halt mode,
● The main oscillator is immediately turned on and the 64 CPU cycle delay is used to
stabilize it.
After this start-up delay, the CPU resumes operation by servicing the AWUFH interrupt. The
AWU flag and its associated interrupt are cleared by software reading the AWUCSR
register.
) To compensate for any frequency dispersion of the AWU RC oscillator, it can be calibrated
t(s by measuring the clock frequency fAWU_RC and then calculating the right prescaler value.
c Measurement mode is enabled by setting the AWUM bit in the AWUCSR register in run
u mode. This connects fAWU_RC to the input capture of the 8-bit lite timer, allowing the
d fAWU_RC to be measured using the main oscillator clock as a reference timebase.
Pro t(s) Similarities with halt mode
te c The following AWUFH mode behavior is the same as normal halt mode:
le u ● The MCU can exit AWUFH mode by means of any interrupt with exit from halt capability
so rod or a reset (see Section 8.4: Active halt and halt modes).
● When entering AWUFH mode, the I bit in the CC register is forced to 0 to enable
b P interrupts. Therefore, if an interrupt is pending, the MCU wakes up immediately.
- O te ● In AWUFH mode, the main oscillator is turned off causing all internal processing to be
) le stopped, including the operation of the on-chip peripherals. None of the peripherals are
t(s o clocked except those which get their clock supply from another clock generator (such
c bs as an external or auxiliary oscillator like the AWU oscillator).
u O ● The compatibility of watchdog operation with AWUFH mode is configured by the
d - WDGHALT option bit in the option byte. Depending on this setting, the HALT instruction
ro ) when executed while the watchdog system is enabled, can generate a watchdog reset.
te P ct(s Figure 25. AWUF halt timing diagram
Obsolete Produ fCPU
le fAWU_RC
Run mode
Obso AWUFH interrupt
tAWU
Halt mode
64 tCPU
Run mode
Clear
by software
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