ST7FLU05MCE View Datasheet(PDF) - STMicroelectronics

Part Name

Description

MFG CO.

ST7FLU05MCE

8-bit low cost, low pin-count MCU for automotive, with single voltage Flash memory, ADC, timers

STMicroelectronics 

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ST7LUS5, ST7LU05, ST7LU09

9

I/O ports

I/O ports

9.1

Introduction

The I/O port offers different functional modes:

● transfer of data through digital inputs and outputs

and for specific pins:

● external interrupt generation

● alternate signal input/output for the on-chip peripherals.

An I/O port contains up to six pins. Each pin (except PA3/RESET) can be programmed

independently as digital input (with or without interrupt generation) or digital output.

ct(s) 9.2

Functional description

du Each port has two main registers:

Pro t(s) ● Data register (DR)

● Data direction register (DDR)

lete uc and one optional register:

so rod ● Option register (OR)

b P Each I/O pin may be programmed using the corresponding register bits in the DDR and OR

- O te registers, with bit X corresponding to pin X of the port. The same correspondence is used for

the DR register.

t(s) ole The following description takes into account the OR register (for specific ports which do not

s provide this register refer to Section 9.6: I/O port implementation). The generic I/O block

c b diagram is shown in Figure 35.

rodu ) - O 9.2.1 Input modes

P t(s The input configuration is selected by clearing the corresponding DDR register bit.

lete uc In this case, reading the DR register returns the digital value applied to the external I/O pin.

so rod Different input modes can be selected by software through the OR register.

b P Note: 1 Writing the DR register modifies the latch value but does not affect the pin status.

O te 2 PA3 cannot be configured as input.

leExternal interrupt function

so When an I/O is configured as Input with Interrupt, an event on this I/O can generate an

Ob external interrupt request to the CPU.

Each pin can independently generate an interrupt request. The interrupt sensitivity is

independently programmable using the sensitivity bits in the EICR register.

External interrupts are hardware interrupts. Fetching the corresponding interrupt vector

automatically clears the request latch. Changing the sensitivity of a particular external

interrupt clears this pending interrupt. This can be used to clear unwanted pending

interrupts.

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