ST7FLUS5MCE View Datasheet(PDF) - STMicroelectronics

Part Name

Description

MFG CO.

ST7FLUS5MCE

8-bit low cost, low pin-count MCU for automotive, with single voltage Flash memory, ADC, timers

STMicroelectronics 

Prev 31 32 33 34 35 36 37 38 39 40 Next

ST7LUS5, ST7LU05, ST7LU09

Supply, reset and clock management

6.3

Reset sequence manager (RSM)

6.3.1 Introduction

The reset sequence manager includes three reset sources as shown in Figure 15:

● External RESET source pulse

● Internal LVD reset (low voltage detection)

● Internal watchdog reset

Note:

A reset can also be triggered following the detection of an illegal opcode or prebyte code.

Refer to Figure 15.

These sources act on the RESET pin which is always kept low during the delay phase.

) The reset service routine vector is fixed at addresses FFFEh-FFFFh in the ST7 memory

t(s map.

uc Figure 11. Reset block diagram

d VDD

t(s) - Obsoolleettee PPrrooduct(s) RESET

RON

Filter

Pulse

generator

Internal

reset

Watchdog reset

Illegal opcode reset(1)

LVD reset

OObbssoolleettee PPrroodduucct(s) - Obs Caution:

1. See Illegal opcode reset on page 99 for more details on illegal opcode reset conditions.

The basic reset sequence consists of three phases as shown in Figure 16:

● Active phase depending on the reset source

● 64 CPU clock cycle delay

● Reset vector fetch

When the ST7 is unprogrammed or fully erased, the Flash is blank and the reset vector is

not programmed. For this reason, it is recommended to keep the RESET pin in low state

until programming mode is entered, in order to avoid unwanted behavior.

The 64 CPU clock cycle delay allows the oscillator to stabilize and ensures that recovery

has taken place from the reset state.

The reset vector fetch phase duration is 2 clock cycles.

Figure 12. Reset sequence phases

Active phase

Reset

Internal reset

64 clock cycles

Fetch

vector

33/124

Share Link: