Interrupts
ST7LUS5, ST7LU05, ST7LU09
7.2
External interrupts
External interrupt vectors can be loaded into the PC register if the corresponding external
interrupt occurred and if the I bit is cleared. These interrupts allow the processor to leave the
halt low power mode.
The external interrupt polarity is selected through the miscellaneous register or interrupt
register (if available).
An external interrupt triggered on edge will be latched and the interrupt request
automatically cleared upon entering the interrupt service routine.
Caution: The type of sensitivity defined in the miscellaneous or interrupt register (if available) applies
to the ei source.
t(s) 7.3
OObbssoolleettee PPrroodduucctt((ss)) -- OObbssoolleettee PPrroodduucct(s) Note:
Peripheral interrupts
Different peripheral interrupt flags in the status register are able to cause an interrupt when
they are active if both:
● The I bit of the CC register is cleared.
● The corresponding enable bit is set in the control register.
If any of these two conditions is false, the interrupt is latched and thus remains pending.
An interrupt request is cleared by doing one of the following:
● Writing ‘0’ to the corresponding bit in the status register
● Accessing the status register while the flag is set followed by a read or write of an
associated register.
The clearing sequence resets the internal latch. A pending interrupt (that is, waiting for
being enabled) will therefore be lost if the clear sequence is executed.
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