ST7LUS5, ST7LU05, ST7LU09
Supply, reset and clock management
Figure 13. Reset sequences
VDD
VIT+(LVD)
VIT-(LVD)
RUN
LVD
reset
Active phase
RUN
External
reset
Active
phase
RUN
Watchdog
reset
Active
phase
RUN
uct(s) External
d RESET
ro source
P t(s) RESET pin
lete duc Watchdog
OObbssoolleettee PPrroodduucctt((ss)) -- OObbssoolete Pro reset
th(RSTL)in
tw(RSTL)out
Watchdog underflow
Internal reset (64 TCPU)
Vector fetch
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