ST7LITE20F2 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
ST7LITE20F2
STMicroelectronics
'ST7LITE20F2' PDF : 166 Pages View PDF
ST7LITE20F2 ST7LITE25F2 ST7LITE29F2
Instruction set
Table 55. Instruction groups (continued)
Group
Instructions
Conditional Branch
JRxx
−
−
−
−
−
Interruption management
TRAP WFI HALT IRET −
−
Condition Code Flag modification SIM RIM SCF RCF −
−
−−
−−
−−
Using a prebyte
The instructions are described with 1 to 4 bytes.
In order to extend the number of available opcodes for an 8-bit CPU (256 opcodes), three
different prebyte opcodes are defined. These prebytes modify the meaning of the instruction
they precede.
The whole instruction becomes:
● PC-2: End of previous instruction
● PC-1: Prebyte
● PC: Opcode
● PC+1: Additional word (0 to 2) according to the number of bytes required to compute
the effective address.
These prebytes enable instruction in Y as well as indirect addressing modes to be
implemented.
They precede the opcode of the instruction in X or the instruction using direct addressing
mode. The prebytes are:
● PDY 90: Replace an X based instruction using immediate, direct, indexed, or inherent
addressing mode by a Y one.
● PIX 92: Replace an instruction using direct, direct bit or direct relative addressing mode
to an instruction using the corresponding indirect addressing mode.
It also changes an instruction using X indexed addressing mode to an instruction using
indirect X indexed addressing mode.
● PIY 91: Replace an instruction using X indirect indexed addressing mode by a Y one.
12.2.1
Note:
Illegal opcode reset
In order to provide enhanced robustness to the device against unexpected behavior, a
system of illegal opcode detection is implemented. If a code to be executed does not
correspond to any opcode or prebyte value, a reset is generated. This, combined with the
Watchdog, allows the detection and recovery from an unexpected fault or interference.
A valid prebyte associated with a valid opcode forming an unauthorized combination does
not generate a reset.
Table 56. Instruction set overview
Mnemo
Description
Function/example
Dst
Src
ADC
ADD
AND
Add with Carry
Addition
Logical And
A=A+M+C
A
M
A=A+M
A
M
A=A.M
A
M
H I NZC
H−NZC
H−NZC
− −NZ−
Doc ID 8349 Rev 5
115/166
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