ST7LITE20F2 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
ST7LITE20F2
STMicroelectronics
'ST7LITE20F2' PDF : 166 Pages View PDF
I/O ports
ST7LITE20F2 ST7LITE25F2 ST7LITE29F2
Caution:
Spurious interrupts
When enabling/disabling an external interrupt by setting/resetting the related OR register bit,
a spurious interrupt is generated if the pin level is low and its edge sensitivity includes
falling/rising edge. This is due to the edge detector input which is switched to '1' when the
external interrupt is disabled by the OR register.
To avoid this unwanted interrupt, a "safe" edge sensitivity (rising edge for enabling and
falling edge for disabling) has to be selected before changing the OR register bit and
configuring the appropriate sensitivity again.
In case a pin level change occurs during these operations (asynchronous signal input), as
interrupts are generated according to the current sensitivity, it is advised to disable all
interrupts before and to reenable them after the complete previous sequence in order to
avoid an external interrupt occurring on the unwanted edge.
This corresponds to the following steps:
1. To enable an external interrupt:
– set the interrupt mask with the SIM instruction (in cases where a pin level change
could occur)
– select rising edge
– enable the external interrupt through the OR register
– select the desired sensitivity if different from rising edge
– reset the interrupt mask with the RIM instruction (in cases where a pin level
change could occur).
2. To disable an external interrupt:
– set the interrupt mask with the SIM instruction SIM (in cases where a pin level
change could occur)
– select falling edge
– disable the external interrupt through the OR register
– select rising edge
– reset the interrupt mask with the RIM instruction (in cases where a pin level
change could occur).
10.2.2
Output modes
Setting the DDRx bit selects output mode. Writing to the DR bits applies a digital value to the
I/O through the latch. Reading the DR bits returns the previously stored value.
If an OR bit is available, different output modes can be selected by software: push-pull or
opendrain. Refer to I/O Port Implementation section for configuration.
Table 21. DR value and output pin status
DR
Push-pull
0
VOL
1
VOH
Open-drain
VOL
Floating
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Doc ID 8349 Rev 5
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