I/O ports
ST7LITE20F2 ST7LITE25F2 ST7LITE29F2
Figure 32. Interrupt I/O port state transitions
01
00
10
11
INPUT
floating/pull-up
interrupt
INPUT
floating
(reset state)
OUTPUT
open-drain
OUTPUT
push-pull
XX = DDR, OR
10.4
10.5
10.6
10.7
Unused I/O pins
Unused I/O pins must be connected to fixed voltage levels. Refer to Section 13.8: I/O port
pin characteristics.
Low power modes
Table 24. Effect of low power modes on I/O ports
Mode
Description
WAIT
HALT
No effect on I/O ports. External interrupts cause the device to exit from WAIT mode.
No effect on I/O ports. External interrupts cause the device to exit from HALT mode.
Interrupts
The external interrupt event generates an interrupt if the corresponding configuration is
selected with DDR and OR registers and if the I bit in the CC register is cleared (RIM
instruction).
Table 25. I/O port interrupt control/wake-up capability
Interrupt event
Event flag
Enable
control bit
Exit from
WAIT
Exit from
HALT
External interrupt on selected
external event
−
DDRx
ORx
Yes
Yes
Device-specific I/O port configuration
The I/O port register configurations are summarized as follows:
Standard ports
Table 26. Ports PA7:0, PB6:0
Mode
Floating input
Pull-up input
DDR
OR
0
0
0
1
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