ST7LITE25F2 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
ST7LITE25F2
STMicroelectronics
'ST7LITE25F2' PDF : 170 Pages View PDF
Supply, reset and clock management
ST7LITE20F2 ST7LITE25F2 ST7LITE29F2
7.5.5
Internal watchdog RESET
The RESET sequence generated by a internal Watchdog counter overflow is shown in
Figure 16.
Starting from the Watchdog counter underflow, the device RESET pin acts as an output that
is pulled low during at least tw(RSTL)out.
Figure 16. RESET sequences
VDD
VIT+(LVD)
VIT-(LVD)
Run
LVD
RESET
Active phase
Run
External
RESET
Active
phase
Run
Watchdog
RESET
Active
phase
Run
External
RESET
SOURCE
RESET PIN
Watchdog
RESET
th(RSTL)in
tw(RSTL)out
Watchdog underflow
Internal RESET (256 or 4096 TCPU)
Vector fetch
7.6
Note:
7.6.1
System integrity management (SI)
The system integrity management block contains the low voltage detector (LVD) and
auxiliary voltage detector (AVD) functions. It is managed by the SICSR register.
A reset can also be triggered following the detection of an illegal opcode or prebyte code.
Refer to Section 12.2.1: Illegal opcode reset for further details.
Low voltage detector (LVD)
The low voltage detector function (LVD) generates a static reset when the VDD supply
voltage is below a VIT-(LVD) reference value. This means that it secures the power-up as well
as the power-down keeping the ST7 in reset.
The VIT-(LVD) reference value for a voltage drop is lower than the VIT+(LVD) reference value
for power-on in order to avoid a parasitic reset when the MCU starts running and sinks
current on the supply (hysteresis).
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Doc ID 8349 Rev 5
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