ST7LITE25F2 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
ST7LITE25F2
STMicroelectronics
'ST7LITE25F2' PDF : 170 Pages View PDF
ST7LITE20F2 ST7LITE25F2 ST7LITE29F2
On-chip peripherals
11.2.6
Register description
Timer control status register (ATCSR)
Read / Write
Reset value: 0x00 0000 (x0h)
7
6
0
0
ICF
ICIE
CK1
CK0
OVF
OVFIE CMPIE
● Bit 7 = Reserved.
● Bit 6 = ICF Input capture flag
This bit is set by hardware and cleared by software by reading the ATICR register (a
read access to ATICRH or ATICRL will clear this flag). Writing to this bit does not
change the bit value.
0: No input capture
1: An input capture has occurred
● Bit 5 = ICIE IC interrupt enable
This bit is set and cleared by software.
0: Input capture interrupt disabled
1: Input capture interrupt enabled
● Bits 4:3 = CK[1:0] Counter clock selection
These bits are set and cleared by software and cleared by hardware after a reset. They
select the clock frequency of the counter.
Table 35. Counter clock selection
Counter clock selection
CK1
CK0
OFF
fLTIMER (1 ms timebase @ 8 MHz) (1)
fCPU
32 MHz (2)
0
0
0
1
1
0
1
1
1. PWM mode and Output Compare modes are not available at this frequency.
2. ATICR counter may return inaccurate results when read. It is therefore not recommended to use Input
Capture mode at this frequency.
● Bit 2 = OVF Overflow flag
This bit is set by hardware and cleared by software by reading the TCSR register. It
indicates the transition of the counter from FFFh to ATR value.
0: No counter overflow occurred
1: Counter overflow occurred
● Bit 1 = OVFIE Overflow interrupt enable
This bit is read/write by software and cleared by hardware after a reset.
0: OVF interrupt disabled.
1: OVF interrupt enabled.
● Bit 0 = CMPIE Compare interrupt enable
This bit is read/write by software and cleared by hardware after a reset. It can be used
Doc ID 8349 Rev 5
79/166
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