STA015 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'STA015' PDF : 44 Pages View PDF
STA015-STA015B-STA015T
ADPCM_DATA_READY
Address: 0x52 (82)
Type: R/W
Software Reset: 0x00
Hardware Reset: 0x00
MSB
LSB
b7 b6 b5 b4 b3 b2 b1 b0
X X X X X X X ADR
ADR: Adpcm Data Ready
This bit signal ADPCM encoded data are ready to
be retrieved.
PLLFRAC_441_H
Address: 0x52 (82)
Type: R/W
Software Reset: 0x00
Hardware Reset: 0x00
MSB
LSB
b7 b6 b5 b4 b3 b2 b1 b0
PF15 PF14 PF13 PF12 PF11 PF10 PF9 PF8
The registers are considered logically concate-
nated and contain the fractional values for the
PLL, for 44.1KHz reference frequency.
(see also PLLFRAC_L and PLLFRAC_H regis-
ters)
ADPCM_SAMPLE_FREQ
Address: 0x53 (83)
Type: R/W
Software Reset: 0x00
Hardware Reset: 0x00
MSB
LSB
b7 b6 b5 b4 b3 b2 b1
b0
XXX
ADPCM_SF
ADPCM_SF: Adpcm Sample Frequency
0x02
0x0A
0x0E
8KHz
16KHz
32KHz
PCMDIVIDER
Address: 0x54 (84)
Type: RW
Software Reset: 0x01
Hardware Reset: 0x01
7
6
5
4
3
2
1
0
PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0
PCMDIVIDER is used to set the frequency ratio
between the OCLK (Oversampling Clock for
DACs), and the SCKT (Serial Audio Transmitter
Clock).
The relation is the following:
SCKT_freq
=
2
OCLK_freq
(1 + PCM_DIV)
23/44
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