STA015 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'STA015' PDF : 44 Pages View PDF
STA015-STA015B-STA015T
FRAME_CNT_L
MSB
LSB
b7 b6 b5 b4 b3 b2 b1 b0
FC7 FC6 FC5 FC4 FC3 FC2 FC1 FC0
FRAME_CNT_M
MSB
LSB
b7 b6 b5 b4 b3 b2 b1 b0
FC15 FC14 FC13 FC12 FC11 FC10 FC9 FC8
FRAME_CNT_H
MSB
LSB
b7 b6 b5 b4 b3 b2 b1 b0
FC23 FC22 FC21 FC20 FC19 FC18 FC17 FC016
Address: 0x67, 0x68, 0x69 (103 - 104 - 105)
Type: RO
Software Reset: 0x00
Hardware Reset: 0x00
The three registers are considered logically con-
catenated and compose the Global Frame
Counter as described in the table.
It is updated at every decoded MPEG Frame.
The registers are reset on both hardware and
software reset.
AVERAGE_BITRATE
Address: 0x6A (106)
Type: RO
Software Reset: 0x00
Hardware Reset: 0x00
MSB
LSB
b7 b6 b5 b4 b3 b2 b1 b0
AB7 AB6 AB5 AB4 AB3 AB2 AB1 AB0
AVERAGE_BITRATE is a read-only register and
it contains the average bitrate of the incoming bit-
stream divided by two. The value is rounded with
an accuracy of 1 Kbit/sec.
SOFTVERSION
Address: 0x71 (113)
Type: RO
MSB
LSB
b7 b6 b5 b4 b3 b2 b1 b0
SV7 SV6 SV5 SV4 SV3 SV2 SV1 SV0
After the STA015 boot, this register contains the
version code of the embedded software.
RUN
Address: 0x72 (114)
Type: RW
Software Reset: 0x00
Hardware Reset: 0x00
MSB
LSB
b7 b6 b5 b4 b3 b2 b1 b0
X X X X X X X RUN
Setting this register to 1, STA015 leaves the idle
state, starting the decoding process.
The Microcontroller is allowed to set the RUN
flag, once all the control registers have been in-
itialized.
TREBLE_FREQUENCY_LOW
Address: 0x77 (119)
Type: RW
Software Reset: 0x00
Hardware Reset: 0x00
MSB
LSB
b7 b6 b5 b4 b3 b2 b1 b0
TF7 TF6 TF5 TF4 TF3 TF2 TF1 TF0
TREBLE_FREQUENCY_HIGH
Address: 0x78 (120)
Type: RW
Software Reset: 0x00
Hardware Reset: 0x00
MSB
LSB
b7 b6 b5 b4 b3 b2 b1 b0
TF15 TF14 TF13 TF12 TF11 TF10 TF9 TF8
The registers TREBLE_FREQUENCY-HIGH and
TREBLE_FREQUENCY-LOW, logically concate-
nated as a 16 bit wide register, are used to select
the frequency, in Hz, where the selected fre-
quency is +12dB respect to the stop band.
By setting these registers, the following rule must
be kept:
Treble_Freq < Fs/2
27/44
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