STA016A View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'STA016A' PDF : 43 Pages View PDF
STA016A
Description :
This register specifies the high cut frequency: fcut(in
Hz)=(TONE_FCUTH+1)*50.
6.14.3 TONE_FCUTL :
b7 b6 b5 b4 b3 b2 b1 b0
Address : 0x7C(124)
Type : RW - ABO
Software Reset : 10
Description :
This register specifies the low cut frequency: fcut(in
Hz) = (TONE_FCUTL+1)*10
6.14.4 TONE_GAINH :
b7 b6 b5 b4 b3 b2 b1 b0
Address : 0x7D(125)
Type : RW - ABO
Software Reset : 12
Description :
This register specifies the gain on high frequencies:
6.15 TABLES
gain(in Db)=(TONE_GAINH-12)*1.5
6.14.5 TONE_GAINL :
b7 b6 b5 b4 b3 b2 b1 b0
Address : 0x7E(126)
Type : RW - ABO
Software Reset : 12
Description :
This register specifies the gain on high frequencies:
gain (in Db)=(TONE_GAINL-12)*1.5. Value of regis-
ter from 0 to 24.
6.14.6 TONE_GAIN_ATTEN :
b7 b6 b5 b4 b3 b2 b1 b0
Address : 0x7F(127)
Type : RW - ABO
Software Reset : 0
Description :
This register specifies the attenuation on global spec-
trum: gain (in dB)=-TONE_GAIN_ATTEN*1.5. Value
of register from 0 to 12.
Table 36. values to configure audio PLL for ofact==256.
This table give values to configure the audio PLL according CRYCK so that to generate a PCMCK == 256*SF.
Register
CRYCK in MHz
10
CRYCK in MHz
14.31818
CRYCK in MHz
14.7456
PLL_AUDIO_PEL_192
42
58
85
PLL_AUDIO_PEH_192
169
187
85
PLL_AUDIO_NDIV_192
0
0
0
PLL_AUDIO_XDIV_192
3
3
0
PLL_AUDIO_MDIV_192
18
12
2
PLL_AUDIO_PEL_176
56
54
0
PLL_AUDIO_PEH_176
16
118
64
PLL_AUDIO_NDIV_176
0
0
0
PLL_AUDIO_XDIV_176
3
2
3
PLL_AUDIO_MDIV_176
17
8
11
34/43
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