STA016A View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'STA016A' PDF : 43 Pages View PDF
STA016A
Table 39. values to configure system PLL for SYSCK.
This table give values to configure the system PLL according CRYCK so that to generate a SYSCK == 50MHz.
or SYSCK == 42.5MHz.
Register
PLL_SYSTEM_PEL_50
PLL_SYSTEM_PEH_50
PLL_SYSTEM_NDIV_50
PLL_SYSTEM_XDIV_50
PLL_SYSTEM_MDIV_50
PLL_SYSTEM_PEL_42_5
PLL_SYSTEM_PEH_42_5
PLL_SYSTEM_NDIV_42_5
PLL_SYSTEM_XDIV_42_5
PLL_SYSTEM_MDIV_42_5
CRYCK in MHz 10
162
11
0
1
19
0
0
0
1
16
CRYCK in MHz
14.31818
0
0
0
1
13
126
223
0
1
10
CRYCK in MHz
14.7456
28
152
0
1
12
100
135
0
1
10
Table 40. index of the Sampling Frequency.
Index
0
1
2
4
5
6
8
9
10
12
13
14
16
17
18
3, 7, 11, 15 or 19
Frequency
48 kHz
44.1 kHz
32 kHz
96 kHz
88.2 kHz
64 kHz
24 kHz
22.05 kHz
16 kHz
12 kHz
11.025 kHz
8 kHz
192 kHz
176.4 kHz
128 kHz
illegal frequency
36/43
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