STA016A
Table 37. values to configure audio PLL for ofact==384
This table give values to configure the audio PLL according CRYCK so that to generate a PCMCK == 384*SF.
Register
CRYCK in MHz
10
CRYCK in MHz
14.31818
CRYCK in MHz
14.7456
PLL_AUDIO_PEL_192
224
108
0
PLL_AUDIO_PEH_192
190
76
0
PLL_AUDIO_NDIV_192
0
0
0
PLL_AUDIO_XDIV_192
1
1
1
PLL_AUDIO_MDIV_192
13
9
9
PLL_AUDIO_PEL_176
42
54
0
PLL_AUDIO_PEH_176
140
118
48
PLL_AUDIO_NDIV_176
0
0
0
PLL_AUDIO_XDIV_176
1
1
1
PLL_AUDIO_MDIV_176
12
8
8
Table 38. values to configure audio PLL for ofact==512.
This table give values to configure the audio PLL according CRYCK so that to generate a PCMCK == 512*SF.
Register
PLL_AUDIO_PEL_192
PLL_AUDIO_PEH_192
PLL_AUDIO_NDIV_192
PLL_AUDIO_XDIV_192
PLL_AUDIO_MDIV_192
PLL_AUDIO_PEL_176
PLL_AUDIO_PEH_176
PLL_AUDIO_NDIV_176
PLL_AUDIO_XDIV_176
PLL_AUDIO_MDIV_176
CRYCK in MHz
10
42
169
0
1
18
56
16
0
1
17
CRYCK in MHz
14.31818
58
187
0
0
5
157
157
0
1
11
CRYCK in MHz
14.7456
85
85
0
1
12
0
64
0
1
11
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