STA306
3.0 CONFIGURATION REGISTER A (ADDRESS 00H)
BIT
D7
D6
D5
D4
D3
NAME
MPC
HPE
BME
IR1
IR0
RST
1
0
0
0
0
D2
MCS2
0
D1
MCS1
1
D0
MCS0
1
3.0.1 Master Clock Select
BIT
R/W
RST
0
R/W
1
1
R/W
1
2
R/W
0
NAME
MCS0
MCS1
MCS2
DESCRIPTION
Master Clock Select : Selects the ratio between the input I2S
sample frequency and the input clock.
The STA306 will support sample rates of 32kHz, 44.1kHz, 48Khz, 88.2kHz, 96kHz, 176.4kHz, and 192kHz.
Therefore the internal clock will be:
– 65.536Mhz for 32kHz
– 90.3168Mhz for 44.1khz, 88.2kHz, and 176.4kHz
– 98.304Mhz for 48kHz, 96kHz, and 192kHz
The external clock frequency provided to the XTI pin must be a multiple of the input sample frequency(fs). The
relationship between the input clock and the input sample rate is determined by both the MCSx and the IRx (In-
put Rate) register bits. The MCSx bits determine the PLL factor generating the internal clock and the IRx bits
determine the oversampling ratio used internally.
Input Sample Rate
fs (kHz)
IR
MCS(2..0)
1xx
011
010
001
000
32, 44.1, 48
00
128fs
256fs
384fs
512fs
768fs
88.2, 96
01
64fs
128fs
192fs
256fs
384fs
176.4, 192
10
64fs
128fs
192fs
256fs
384fs
3.0.2 Interpolation Ratio Select
BIT R/W RST NAME
DESCRIPTION
3
R/W
0
4
R/W
0
IR0 Interpolation Ratio Select : Selects internal interpolation ratio based on input I2S
IR1
sample frequency
The STA306 has variable interpolation (oversampling) settings such that internal processing and DDX output
rates remain consistent. The first processing block interpolates by either 4 times, 2 times, or 1 time (pass-
through). The IR bits determine the oversampling ratio of this interpolation.
Table 2. IR bit settings as a function of Input Sample Rate.
Input Sample Rate Fs
IR(1,0)
1st Stage Interpolation Ratio
32kHz
00
4 times oversampling
44.1kHz
00
4 times oversampling
48kHz
00
4 times oversampling
88.2kHz
01
2 times oversampling
96kHz
01
2 times oversampling
176.4kHz
10
Pass-Through
192kHz
10
Pass-Through
11/33