STA306 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'STA306' PDF : 33 Pages View PDF
Table 4. Interface format as a function of SAO bits.
SAO(2..0)
Interface Format
000
I2S
001
Left-Justified Data
010
Right-Justified 16-bit Data
011
Right-Justified 18-bit Data
100
Right-Justified 20-bit Data
101
Right-Justified 24-bit Data
STA306
BIT
R/W
RST
NAME
DESCRIPTION
6
R/W
0
SAOFB Determines MSB or LSB first for all SAO formats;
0 – MSB First
1 – LSB First
3.5 Configuration Register F (address 05h)
BIT
D7
D6
D5
D4
NAME
EAPD
RST
0
D3
D2
D1
D0
AME
COD
SID
PWMD
0
0
0
0
BIT
R/W
RST NAME
DESCRIPTION
0
R/W
0
PWMD PWM Output Disable: 0 – PWM Output Normal
1- No PWM Output
1
R/W
0
SID Serial Interface(I2S Out) Disable: 0 – I2S Output Normal
1- No I2S Output
2
R/W
0
COD Clock Output Disable: 0 – Clock Output Normal
1- No Clock Output
3
R/W
0
AME AM Mode Enable : 0 – Normal DDX operation.
1 – AM reduction mode DDX operation.
The STA306 features a DDX processing mode that minimizes the amount of noise generated in frequency range
of AM radio. This mode is intended to be used when DDX is operating in a device with an AM tuner active. The
SNR of the DDX processing is reduced to ~83dB in this mode, which is still greater than the SNR of AM radio.
BIT R/W RST NAME
DESCRIPTION
7 R/W 0 EAPD External Amplifier Power Down:
0 – External Power Stage Power Down Active
1 - Normal Operation
This output bit, on pin 51 of the device, is used to mute the DDX Power Devices for Power-Down.
3.6 Master Mute Register (address 06h)
BIT
D7
D6
D5
NAME
RST
D4
D3
D2
D1
D0
MMUTE
0
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